EE Times Current

EE Times Current

EE Times Current provides a deep dive into the most compelling stories in the electronics industry. Tune in to keep yourself current on what matters to design engineers and other tech industry professionals

Beyond PPA: How Foundation IP Enables Predictable Execution and Lower TCO for AI-Era SoCs
EE Times Current
Beyond PPA: How Foundation IP Enables Predictable Execution and Lower TCO for AI-Era SoCs

Recent Episodes

Oct. 7, 2026

Beyond PPA: How Foundation IP Enables Predictable Execution and Lower TCO for AI-Era SoCs

As AI-driven SoCs move to advanced process nodes, design complexity, development cost, and execution risk are rising sharply. In this episode, Synopsys Executive Director of Product Management Ravi Todi explains why competitive power, performance, and area (PPA) are no longer sufficient on their own. Success in the AI era also depends on predictable execution and disciplined management of total cost of ownership (TCO) across the full SoC lifecycle. The discussion highlights how a holistic, sili
Sept. 25, 2026

Can Disaggregated Memory Reshape AI Inference?

In this podcast, EE Times' Sally Ward-Foxton talks to Majestic Labs’ Sha Rabii about why AI's shift toward inference, long context, and agentic workloads could require a fundamentally different compute-memory architecture.
Sept. 18, 2026

Why Computing With Time Gives Neuromorphic AI an Edge

In this month's Brains and Machines, Dr. Ryad Benosman discusses event-based vision, retinal prosthetics, and neuromorphic startups with Dr. Sunny Bains of University College London. A co-founder of Prophesee, he explains why he believes AI's future must come from neuromorphic engineering. Discussion follows with Dr. Giulia D’Angelo from the Czech Technical University in Prague and Professor Ralph Etienne-Cummings of Johns Hopkins University.
Sept. 4, 2026

Where Software Meets Silicon: A Digital Twin Playbook

As systems become more software-defined, the traditional development model of waiting for hardware before serious software validation begins is no longer sustainable. Software teams need platforms earlier. Hardware teams need realistic workloads sooner. Verification teams need better ways to expose system-level issues before tapeout. We will look at how digital twins are becoming the shared foundation for this new HW/SW co-development model. Using virtual platforms, hardware emulation, and FPGA
Aug. 26, 2026

Trust at Scale: The Next Challenge for AI-Driven Semiconductor Development

Artificial intelligence is accelerating semiconductor development, but more compute, more automation, and more engineering data do not automatically create better decisions. As design and manufacturing workflows become increasingly AI-enabled, a new constraint is emerging: trust. In this episode, Dr. Jim Shiely builds on themes from his Patterning the Singularity leadership work to explore the semiconductor industry’s “trust bottleneck” and why trustworthy engineering intelligence is becoming es
Aug. 25, 2026

Do Spikes Need Common Language for Sensing and Learning?

On this month's episode of Brains and Machines, five engineers debate neuromorphic sensing and learning. Recorded at the Neuromorphic Hardware and Algorithms conference at the University of Sussex, the panel explores whether events and spikes are the right framework for integrating sensor modalities, motor control, and learning across systems. They also examine commercial directions and revisit the perennial question: what is neuromorphic engineering? The panelists are: Dr. Chiara Bartolozzi (